1. Field
The embodiments relate to a simulation method and a simulation apparatus applied to a multicore processor, a multiprocessor or a multi-master/slave device.
2. Description of the Related Art
Conventionally, simulators have been used in SoC (System on a Chip) software development, for example. Simulation can involve rerunning a simulator to reproduce states of the processor. However, to develop large-scale software projects on a simulator, development periods become very long due to lengthened rerunning times.
To deal with this problem, for example conventionally a restore point is set at a given time point, and information required to reproduce the state of the processor at the given time point (information relating to memory, registers, buffers, information from inside other processors, data and status information from surrounding circuits, etc.) is stored, and subsequently read and used to reproduce processor operations.
The technologies for storing information at the restore point are becoming more important in the development of software for use in processors such as multiprocessors and multicore processors including a plurality of CPU (Central Processing Unit) cores, which have appeared on the market in recent years.
FIG. 1 illustrates a flow of processing for a case in which a conventional simulation method using a restore point is applied to a multicore processor which is operating using a single thread.
The following describes an example simulation in a multicore model having core models PE0 and PE1 corresponding to two processor cores.
The simulation can make use of an Instruction Set Simulator (ISS) (not shown).
When the simulation begins, the simulator performs an execution judgment (operation S80). In the case of execution, the simulator can set restore points (common restore points) in surrounding devices, for example shared by the core models PE0 and PE1, and can store corresponding states (information relating to memory usage by the surrounding devices, for example) (operation S81).
Then, after setting restore points in the core model PEO and storing a state of the core PEO model (operation S82), the simulator executes a core model PEO instruction (operation S83).
In the ISS, the instruction execution can be performed with a function such as an exe_loop.
FIG. 2 is a flowchart illustrating processing of the exe_loop function.
The flowchart illustrates an example in which a number of execution instructions (execution operations) in the exe_loop function are specified, and the instructions are executed one at a time.
Note, however, that since the number of instructions in the exe_loop can depend on the architecture, the simulator may execute a plurality of instructions simultaneously rather than executing a single instruction at a time. Here, in the interest of simplicity, the description is limited to a single instruction in a single loop.
First, the simulator can set a local execution (LSE) operation to “0” (operation S821). Next, the simulator judges whether the LSE equals the number of operations set by a user (US) (operation S822). When the two are equal, the simulator ends instruction execution in the core model PEO. When the two are unequal, the simulator fetches an instruction (operation S823), and decodes and executes the fetched instruction (operation S824). Thereafter, the simulator increments the LSE (operation S825), performs exception processing (operation S826), and repeats the processing beginning at operation S822.
As seen in FIG. 1, on completion of instruction execution in the core model PE0, the simulator can set a restore point in the core model PE1 and can store a state of the core model PE1 (operation S84), and performs instruction execution for the core model PE1 in a manner similar to that shown in FIG. 2 (operation S85). Thereafter, the simulator returns to operation S80 and repeats the above-described processing.
FIG. 3 is a diagram illustrating an example of a single thread operation in the multicore processor.
In the case of a single thread, the core models PE0 and PE1 take turns to perform a single processing unit (US of FIG. 2) of instruction execution. Before performing the respective processing in the core models PE0 and PE1, the simulator can set restore points A0, B0, C0, A1, B1, C1, and store states of the PE0 and PE1 cores at each of the restore points.
However, there is a problem in that the conventional simulation methods are largely intended to be applied to single core devices, and are not appropriate for multicore processors, multiprocessors or multi-master/slave devices. For example, the methods for storing states at restore points corresponding to the single threads shown in FIGS. 1 through 3 have problems of being efficiently finding deadlocks, I/O races, multiple access to shared variables, for example, which can occur when a plurality of core models perform processing in parallel.
According to an aspect of an embodiment discussed herein a simulation method includes setting restore points in each of a plurality of core models for executing threads using parallel processing; and the storing information for reproducing a state of each of the plurality of core models at the restore points.
Additional aspects and/or advantages will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention.